Abstract
In communication systems with the orthogonal frequency division access (OFDMA) technology, multiple users can share the same bandwidth offered by only one base station, which means the resource allocation technique is highly emphasized. Since each user allocates partial bandwidth, power consumption can be reduced by performing partial fast Fourier transform (FFT). In this work, we proposed the algorithm of resource block allocation technique. According to the proposed algorithm, we designed a low-cost and low-power FFT structure based on cached memory; besides, a scalable and power-aware processing element was adopted for twiddle factor multiplication. The proposed butterfly processor can support the radix-3 operation in order to perform 1536-point FFT in the mode 5 of the 3GPP long term evolution (3GPP-LTE) standard. Moreover, the block-floating point (BFP) algorithm was applied to acquire better signal-to-quantization-noise ratio (SQNR). Since the energy dissipation is correlated with operational cycles, we proposed a reconfigurable architecture of the FFT processor which is capable of reducing operational cycles by switching controlling circuits depending on different conditions. Finally, the cached-FFT processor was implemented with TSMC 0.18um 1P6M CMOS technology, and the measurement of energy dissipation ranged from 1.23 to 4.24nJ per FFT point.