Abstract
In this thesis, we present a methodology to generate floorplan-aware bus-based communication architectures. The methodology aims to minimize communication energy while the user-specified performance constraints can be satisfied. Our methodology can be roughly divided into two steps. The first step is to generate an initial solution through a floorplanning process. In this step, for each candidate floorplan, we will choose a bus architecture first, and then estimate its communication energy and performance. Among the bus architectures which are accepted in this step and satisfy user-specified performance constraints, the one with smallest communication energy will be selected as the initial solution. In the second step, our methodology will further try to search for better solutions (with even smaller communication energy) based on the initial solution through a simulated annealing based refinement process. We have implemented our methodology and the experimental results show that only 5% performance degradation is required to make at least 59.78% reduction of communication energy. This indicates that our methodology is very effective. On the other hand, our methodology is also efficient because the bus architecture of each test case (containing up to 15 IP cores) can be generated in a few minutes.