Abstract
In the VLSI design process, a design implementation often needs to be corrected because of new specifications or design constraint violations. This correction process is referred to as engineering change (EC). Usually, an EC problem is resolved by using spare cells, which have been inserted into the unused spaces of a chip. In this thesis, we propose an iterative method to generate feasible mapping solutions for an EC problem considering spare cells whose inputs may be tied to Vdd or Gnd, called constant insertion. Applying constant insertion can increase the cells’ flexibility in aspect of functionalities, so we do not necessarily have to use far-away cells just for some specific types. In addition, we propose a method to construct a mapping solution using spare cells considering routing or timing issues. Our experimental results show that the area required to find a feasible mapping solution with constant insertion is only 79% of the area without using constant insertion, and the wire length reduction with constant insertion is up to 27%.