Abstract
In the VLSI design process, the design change happens often due to new specifications or design constraint violations. This correction process for the new specification is known as engineering change (EC). Practically, the EC problem is usually resolved by using spare cells, which are inserted into the unused spaces of a chip. Because the spare cells are pre-placed, the usage of spare cells for EC is limited. In this thesis, we propose an iterative way to generate mappings of EC equations satisfying the quantity constraint of spare cells. On average, our method can generate up to 73% of mappings that are satisfy the quantity constraint.