Abstract
This work mainly aims to enhance drain current for a high-k material based FINFET device by stacking additional similar high-k material, accompanied by other merits such as (1) higher transconductance, (2) lower threshold voltage（Vt）, (3) less charge trapping, (4) superior wafer-level thickness uniformity, (5) higher capacitance density and (6) less threshold voltage shift after bias temperature instability（longer BTI lifetime）, etc.. The first part of this work is about how is the phenomenon of stacking high-k material two on high-k material one as total gate oxide layer in MOSFET structure. The whole process includes growing chemical oxide（SiOx）, stacking high-k material one followed by stacking high-k material two, and then first electrode as capping layer followed by rapid thermal annealing (RTA) in order to crystallize; finally, a series of electrodes with different thickness aiming to modulate threshold voltage to fit in the need of each N／PMOSFET. The second part is to discuss what the performance is if the stacking sequence is different from the first part. We can observe that the drain current enhancements of these two experiments are different. The enhancement about stacking high-k material two on high-k material two is higher than that with different sequence. In the first part, it will show not only electrical properties, but also physical properties to confirm the merits about why the drain current got promoted and other better electrical properties. In this experiment, we use stacking high-k material two on high-k material one to get not only enhanced drain current, but other better electrical properties such as lower subthreshold swing（SS）, smaller drain induced barrier lowering（DIBL）, better tolerance against constant voltage stress at high temperature or better bias temperature instability（BTI）.