Abstract
This thesis extends a transaction-splicing technique for slave-to-slave transfers on the Serial Peripheral Interface (SPI) bus. Transaction-splicing technique can completely overlap in the bulk transfer, thereby nearly doubling the performance of standard SPI bus transaction. Although direct memory access (DMA) controllers cannot perform slave-to-slave transfers without going through the memory, it can decrease the MCU overhead of SPI bus transactions. The combination of splicing transactions and involving DMA is more than quintuples the performance of standard SPI bus transaction. It also decreases energy consumption and does not need any memory to cache data. We describe a real implementation with minimal hardware and software overhead while retaining full compatibility with existing SPI devices. It is implemented with a dedicated CPLD, and it can be integrated into a chip such as a microcontroller with few minimal additional cost of only a few logic cells. We present real-world case studies including a 12-lead ECG system, which is sorely in need of enhanced SPI when implemented using low-end MCUs, which would otherwise have plenty of performance without the SPI bottleneck. By using low-end MCUs, it can enable power and cost savings, and the performance of SPI bus transactions with our work is higher than that of high-end MCUs. The evaluation can present about 450% improvement in latency and throughput. By eliminating this bottleneck in virtually all SPI-based designs, we are able to save power while meeting both latency and throughput requirements.