Abstract
With the fast development pace of deep submicron technology comes a rapid growth in the size and density of semiconductor memory. However, keeping a high level of yield and reliability for memory products becomes increasingly difficult. Both the redundancy repair and Error Correction Code (ECC) techniques have been widely used for enhancing the yield and reliability of memory chips. Specifically, the redundancy repair and ECC techniques are conventionally used to repair or correct the hard faults and soft errors, respectively. In this paper, we propose an integrated ECC and redundancy repair scheme for memory reliability enhancement. Previous works emphasized yield improvement as they combined redundancy repair and ECC schemes, while we develop a method to permanantly repair hard errors in the field so that more soft errors can be tolerated without chip failure. Our approach identifies the hard faults and soft errors during the memory normal operation mode, and repairs hard faults during the memory idle time as long as there are unused redundant elements. A method for evaluating the memory reliability is also developed. Experimental results show that the proposed approach is effective, e.g., the MTTF of an 8K 64 memory is improved by 1,412 hours (7.1%) with our integrated ECC and repair scheme. In addition, the development of deep submicron technology causes the semiconductor memory to become larger and denser. In order to maintain high reliability and quality for memory products, ECC buth serves as a soft error correction and plays an important role in reliability enhancement to tolerate other forms of hard errors. However, double-error correctable (DEC) ECC has rarely been used in memory designs because of its high cost in parity area overhead and the complex calculation process. In this paper, we also propose a low-cost double-error correctable scheme without expanding the number of parity bits required in traditional single-error correctable and double-error detectable (SEC-DED) ECC. Experimental results show that the proposed method has a low area overhead with no increase in the decoding cycles compared to conventional double error correctable and triple-error detectable (DEC-TED) ECC (BCH code).