Abstract
With the development of silicon technology, the need of portable multimedia and communication devices is increasing fast day by day, which dominate people’s daily life. The digital signal processing algorithm, such as video and audio codec, voice filtering, and error correction, are also changing in a fast pace. To quickly develop new products with compatibility of latest specifications and algorithm without sacrificing its efficiency, more and more portable device vendors choose DSP solution. Seeing this trend, the SoC Technology Center (STC) in ITRI, started to develop the first VLIW DSP in Taiwan, called PAC (Parallel Architecture Core) DSP. The objective of PACDSP is to provide portable device vendors a complete solution, and to become the best development platform. In this paper, through the research on PACDSP kernel architecture, we have developed an efficient implementation of the evaluating algorithm kernels. We describe our implementations on PACDSP through algorithm flows, data parallelization on both clusters, the relationship between combination of instructions and hardware architecture, and algorithm-level optimizations, from the view of software programmers. Then we compare the cycle count and code size results with the existing DSPs, analysis the impact of PACDSP kernel architectures and instruction sets on our implementations, at last we put forward our suggestions to PACDSP architecture.