Abstract
Modern General Purpose Graphic Processers Units (GPGPU) have been widely used in high performance computing. The massive multithreading architecture of these GPGPUs makes them ideal for data parallel programming. However, this also stresses the memory and the interconnection to/from the memory beyond that from the state-of-the-art Chip Multiprocessors (CMPs). Considering the memory access behaviors in data parallel computing, a viable direction to solve the memory stress problem is to improve the row buffer hit rate of the DRAM. A high hit rate implies fewer replacements of the row buffer and thus higher DRAM performance. Previous approaches considered rearranging the memory requests at the memory controller to increase the row buffer hit rate. The problem is that the window of requests that can be considered for rearrangement is too narrow and the memory controller becomes complicated and affect the critical path. Since the massive multithreading architecture of GPGPUs can better hide memory access latencies, we thus exploit in this thesis the novel idea of rearranging the memory requests in the network-on-chip (NoC). By coalescing memory requests destined for the same row of the DRAM together in the routers of the NoC, memory requests are already in proper order for continuous row buffer hits when they arrive at the memory controller. To study the feasibility of this idea, we have designed an expanded NoC router that supports packet coalescing and evaluated its performance extensively. Evaluation results show that this NoC-assisted design strategy can indeed improve the row buffer hit rate in the memory controllers. Unfortunately, for the benchmarks studied, our design only improves the whole system performance under specific conditions. We conduct in-depth investigations for the possible causes and study ways to mitigate the problems.