Abstract
As the feature size of the semiconductor technology shrunk to nanometer scale, the distance between source and drain of a MOSFET becomes so short such that the gate lose full control of the channel, and thus there is significant leakage current even when gate is grounded. FinFET technology has been adopted to solve this leakage problem. However, FinFET’s 3D structure incorporates significant parasitic capacitance and resistance and that can have larger impacts on circuit performance. To study the dominating factor of the impacts, asymmetric FinFET transistors have been constructed and simulated extensively. It confirms that parasitic resistance and capacitance contribute differently for the source drain terminals. Using this information, the FinFET gate layout is reviewed and two approaches to reduce the parasitic resistance impacts are proposed. One is move the VIA0 position to the center and the other is to increase the number of VIA0. Both approaches were verified by silicon test chips. Asymmetric FinFET transistor layouts that can trade off performance and area have also been developed. However, due to design rule constraints these layouts have not been verified.