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Fast Architecture-Level Synthesis of Fault-Tolerant Flow-Based Microfluidic Biochips
Thesis

Fast Architecture-Level Synthesis of Fault-Tolerant Flow-Based Microfluidic Biochips

Wei-Lun Huang
Masters, 國立清華大學, 資訊工程學系
2016

Abstract

微流體生物晶片 可容錯 Microfluidic Biochips Fault-Tolerant
Microfluidic-based lab-on-a-chips have emerged as a popular technology for implementation of di erent biochemical test protocols used in medical diagnostics. However, in the manufacturing process or during operation of such chips, some faults may occur that leads to damage of the chip, which in turn results in wastage of expensive reagent fluids. In order to make the chip fault-tolerant, the state-of-the-art technique adopts simulated annealing (SA) based approach to synthesize a fault-tolerant architecture. However, the SA method is time consuming and non-deterministic with over-simplified model that usually derive sub-optimal results. Thus, we propose a progressive optimization procedure for the synthesis of fault-tolerant flow-based microfluidic biochips. Simulation results demonstrate that our method is ecient compared to the state-of-the-art techniques and can provide e ective solutions in 88% (on average) less CPU time compared to state-of-the-art technique over three benchmark bioprotocols.

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