Abstract
As we enter the deep submicron age, the continuous improvement of manufacturing technologies has made SoC possible. However, it also brings a lot of challenges in testing. Higher pin count will make it more difficult to probe the dies on the wafer. At speed test is harder due to higher frequency of new SoC products, making it more difficult to maintain the fault coverage and yield. Meanwhile, higher test parallelism is still needed in mass production. Traditional test methodology will be harder and harder to catch up with the increased speed of new process. We thus need to develop new test methodologies to solve tomorrow’s test problems. In the HOY project recently defined at NTHU, a wireless testing methodology is proposed. Based on the HOY concept, we first develop economics models for both the traditional test and HOY wireless test. We consider test cost, manufacturing cost, and development cost in cost model. With the models and some assumptions, we show that HOY will be better than traditional test, so far as the area overhead stays low. We also show that when the process technology continuous to improve, HOY will gain more benefits. A new production test flow is developed to increase the test efficiency, fault coverage and yield. We also propose a parallel testing method to reduce test time. Using our parallel testing method in HOY, the test time will be reduced by more than 80%. Finally, we implement an experimented wireless testing platform using the Bluetooth tool kit and our memory BIST compiler (BRAINS). Experimental results show the feasibility of the HOY concept. 1