Abstract
Flash memory is a nonvolatile semiconductor memory which will not lose stored data after removed the power. Flash memory can be programmed or erased electrically on-line, and retains its stored data for a long time, so it is highly suitable for portable storage devices. Flash memory can be found everywhere in 3C products nowadays, for example, mobile phones, DSC, MP3 players, Flash disks, CF cards etc. The capacity of a single Flash memory chip can up to 8Gbit at present. With the increasing capacity, the test time becomes longer and failure analysis becomes more difficult. Thus, systematic methodologies of test time reduction and diagnosis will improve the yield and reduce the test cost for mass production. In this thesis, we applied the diagnostic methodology that we developed for RAM to Flash memory, modifying as needed. Next, we built an electric model of Flash memory array, then injected defects and performed faulty circuits simulation by using a diagnostic test algorithm. After simulating faulty circuits, we use fault-pattern based diagnostic approach in Flash memory. Finally, we generated the defect dictionary of Flash memory. The resolution of our methodology reached 83.3% in NOR type Flash memory, and 100% in NAND type Flash memory. Next, we proposed a systematic approach to reduce the test time of Flash memory. The test items of Flash memory are much different to RAM. It is because the write operations (erase and program) of Flash memory take a long time. To minimize the test time, there aren’t many Marchlike patterns applied in Flash memory test in industry. Based on our approach, we can reduce the test time without losing fault coverage. We developed an automatic test time reduction tool according to our methodology, and applied it to an industrial case to further reduce total test time by 7%.