Abstract
Flash memories are a type of non-volatile memory based on floating-gate transistors. The use of commodity and embedded Flash memories are growing rapidly as we enter the system-on-chip (SoC) era. Conventional fault models and tests for Flash memories are usually ad hoc, and the test procedure is developed for a specific design. We propose a set of disturb fault models that are derived from the IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays. We also propose improved March-like algorithms (i.e., March-FT) for both bit-oriented and word-oriented Flash memories to cover the disturbance faults as well as conventional faults. Besides, a novel Flash memory fault simulator (called RAMSES-FT) is developed to analyze the fault coverage of the test algorithms. The fault simulator is a key component for the test pattern generation tool TAGS, which produces a test to target the fault set that the user specifies. Based on March-FT, we have designed a built-in self-test (BIST) circuit which is suitable for both the commodity Flash memory and embedded Flash core. Finally, we present the BIST designs for two industrial Flash memories, and show the area overhead that is only about 3% for a medium-sized Flash memory.