Abstract
As the semiconductor process keeps scaling down and IC designs get bigger and faster, uncertainty is becoming one of the greatest challenges for the semiconductor industry. Unexpected and unpredictable behavior of devices often leads to poor quality and reliability. Thus, low-cost test techniques that improve die sorting accuracy are critical for advanced devices. Nonvolatile memory (NVM) has become one of the most rapidly growing market in the semiconductor industry, and flash memory is currently the most popular NVM. However, large capacity, high density, and a complicated cell structure make flash memory cell behavior difficult to predict precisely, thus the uncertainty problem is more serious than other IC devices. It can be complicated even when the dies are tested on the same wafer, as cells in different blocks may call for different test conditions due to geometric process variations. As a fast, easy-to-use solution, we propose a sample classification method. The method is applied to die sort, speed sort, and operation time extraction for diagnosis of flash memory. It is effective not only for flash memory testing, but also for other types of circuits facing similar test problems. Experimental results show that this method efficiently and accurately solves the flash memory die sort problem . The test time is greatly reduced—from 8,817 ms to 718 ms for an industrial chip. Moreover, the proposed approach is suitable for design-for-testability (DFT) implementation. In this work, we propose a built-in self-test (BIST) circuit which supports speed sort and operation time extraction, and can easily be integrated with a commodity or embedded memory.