Abstract
3D integrated circuits can eliminate the effect by using intra-layer interconnects. However, thermal issue in 3D ICs becomes much more severe than in 2D ICs because thinned silicon substrate of each stacked die reduces the heat spreading effect and makes power density to increase due to heat stacking effect. Besides, the bonding material and the back-end-of-line dielectric are heat barriers to heat conduction. High temperature and temperature gradient will deteriorate the reliability and reduce the performance. Therefore, the thermal performance in 3D ICs needs to be considered in early design time and thermal analysis plays an important rule in the 3D IC design. Floorplan-level thermal analysis for 3D ICs can provide fast approximation for temperature distribution on each stacked die and provide indications for the thermal management to avoid inter-die hotspot interaction and heat stacking effect in early design time. In this work, we combined the analytical method and numerical method for floorplan-level thermal analysis and proposed a gate-level power evaluation method for both transient and steady-state thermal analysis. Furthermore, We used empirical function to evaluate the effective thermal conductivity of BEOL layers which is accurate than the average weighted thermal conductivity used in many researches. We constructed a homogeneous multi-core architecture by using OpenRISC IP cores in 3D-SIC as our thermal model for both transient and steady-state thermal simulation by HotSpot5.0. From the simulation results, we found that the hotspots can occur at the locations without high power sources and are influenced by the hotspots in other tiers. Wafer thinning technology worsens thermal performance in 3D ICs. Furthermore, BEOL layers and bonding layers with low-thermal-conductivity materials are heat barriers to heat conduction and induce larger hotspot footprint and higher peak temperature if with larger thickness. However, bonding layer with TSV insertion can improve thermal performance dramatically. The underestimation of the peak temperature in the top die is 5.88K if without taking BEOL and TSV power into account. Besides, we compared the average weighted thermal conductivity of BEOL layers to our method and caused 1.8K underestimation of the peak temperature in the top die because BEOL layers dominate the vertical temperature gradient.