Abstract
As the semiconductor technology continues to shrink, significant gate leakage current is observed, especially when the devices are under stress for a long time. In this situation, traps may accumulate in the oxide and increases the leakage current. As this time, the time dependent dielectric breakdown(TDDB) is becoming an important issue for technology development. The goal of this thesis is to study the impact of gate tunneling current to circuit performance. For easy simulation, Fowler-Nordheim tunneling current model is applied. The 4 different locations of the tunneling current are studied: uniform across the entire gate oxide, gate to drain tunneling, gate to source tunneling and gate to channel tunneling. The impacts of theses tunneling current to circuit operation are extensively simulated using mixed level (device and circuit levels) simulation tool. Mixed level simulations need extensive computation resources and may not be practical in circuit design with large number of transistors, thus a simplified model is sough for. It is a common practice to represent the gate tunneling current by a resistor connecting gate to source or gate to drain. The second part of the thesis tries to find such a simple transistor model to speed up simulation and with reasonable accuracy. However, it is found no such model possible with simple resistor. More researches are needed to construct the circuit level model for TDDB simulations.