Abstract
With the process development, transistors become smaller and more complicated.In 16/14 nm process, FinFETs make a huge progress in electronics industry. Layout migration is an important task in design reuse. In order to migrate the process from 28/20 nm to sub-16 nm, we need to use FinFETs, which make DRC rules change a lot. One of the DRC rules added in FinFETs is that all gates must be positioned on the grid lines. So far, there are no tools reported for migration to the sub-16 nm process automatically. If we want to achieve this goal, one issue we need to tackle will be how to eciently align gates to grid lines. Therefore, we propose in this thesis an approach to address this issue so as to facilitate the migration of a layout to the FinFET technology.