Abstract
Digital video covers a wide range of video applications such as High Definition DVD, Camera Phone, Digital TV and others. And H.264/AVC has multiple advantages such that it can provide a better compression performance than previous standards. The advantages for H.264/AVC are the following : (1) Bit-rate saving : Comparing with H.263 and MPEG-4, it can achieve about 50% bit-rate reduction. (2) High quality : H.264/AVC can offer a certain good video quality even in a low bit-rate channel. (3)Error resilience : H.264/AVC provides several error resilience tools to deal with the problem of packet-loss. (4) NAL : To use the Network Adaptation Layer, H.264/AVC bitstream can transmit on different network easily. However, H.264/AVC video coding is considerably more complicated than precious standards, and also needs much more decoding information. Therefore, how to design a highly efficient real-time decoder and to reduce power consumption are most important things in the field of H.264/AVC code design. In this thesis, data reuse and operation time reduction are emphasized in the design. As for the CAVLC Decoder unit, we propose two methods to reduce process cycles and level table storage; for the Inverse Transform unit, we use several matrix identities to reduce process cycles; as to the Intra Prediction unit, we propose a new architecture of intra prediction generator to support most prediction modes except Intra16x16 plane mode, and then we also propose a simple way to implement Intra16x16 plane modee. The Inter-Prediction unit highly exploits the data reuse technique between interpolations of neighboring blocks to save process cycles. Finally,for the Deblocking-Filter unit, we propose a three stage pipeline architecture using three internal memory to store the reusing data to reduce process cycles. A prototype design is implemented by Artisan 0.18um standard CMOS cell library with UMC 0.18um technology. The total gate count is about 248K synthesized at 120MHz. The maximum processing capability is an 1920x1080 4:2:0 30Hz video. Totally, about 12K on chip memory are required. The average power consumption is 156.17mW when operating at 120MHz under 1.8V power supply.