Abstract
In our daily life, digital video is always an important part for us. Among television, computer monitor, cell-phone and palm game player, these equipments all need video technology to display what they are showing. Especially video coding has become more significant. Some popular techniques of video coding, like MPEG-2, MPEG-4, H.263 and H.264/AVC, have great impact on video quality. Among them, H.264/AVC has been paid most attention recently. H.264/AVC is the latest international video coding standard. It has precise manner of prediction and high compression rate that can achieve high visual quality and greatly reduce required bits in transmission. Because of its complex algorithm, it can achieve high performance. Like intra-prediction, integer-pixel and quarter-pixel motion estimation and context-adaptive binary arithmetic coding (CABAC), they have great improvement on video quality and compression. But due to its high complexity, the hardware VLSI implementation is very hard to be realized. De-blocking filter is an important component of H.264/AVC to reduce the block artifacts. It filters the reconstructed frame to improve video quality of human visual perception. With accessing reconstructed frame data continuously, the processing speed has become one bottleneck for real-time application. Also, the memory usage beside the de-blocking filter for reducing cost needs to be concerned. In this thesis, we propose a new architecture for de-blocking filter in H.264/AVC. New filtering order and overlapped bi-directional filtering will be presented. Two one-dimensional FIR filters are used for horizontal and vertical filtering. The pixel data can be fully reused. Maybe the logic area of the filter is larger, but for reducing the processing time and real-time application, our design may have real merits.