Abstract
H.264/AVC is the latest video compression standard. It achieves a significant improvement in bit-rate saving and rate-distortion performance compared with all existing compression standards. However, H.264 complicated encoding process can not guarantee feasibility in real-time coding implementation; in addition, huge computation will cause huge power-consumption. Therefore, from a conservative view, it will face a big challenge for becoming unpopular even it has superior performance. The object of this thesis is to optimize the architectures of H.264 motion estimation and to reduce its computational complexity. The architecture of H.264 motion estimation is based on low-power algorithm. Flexible architecture is designed such that the use of H.264 in different applications can be adjusted by easy-recombining, and it will also possess real-time coding capability. In addition, we propose a H.264 reconstruction architecture with low-complexity, which produces the reordering coefficients and rebuilds reconstructed frame respectively. Finally, we propose baseline encoder architecture with three-stage pipeline scheme, which effectively incorporates and manages specific stages for real-time coding. Xilinx FPGA platform simulation demonstrates the real-time capability of proposed H.264 ME architecture. From architecture simulation, we observe that integer motion compensation PSNR could be improved about 3 dB by quarter-pixel refinement. And proposed low-power strategies for motion estimation architecture could substantially save power over 70% without losing original quality. Finally, the proposed baseline encoder architecture rebuilds color reconstruction frame with constant quality of 45dB basically and ensures that decoder displays stable decoding frame.