Abstract
Recently, many video encoding standards are applied to the communication devices. In most compression standards, such as H.263, H.26L, MPEG2 and MPEG4, motion estimation exploits large amount of computation power. An emerging video encoding technique, H.26L, achieves a bit rate reduction of about 30% with the same quality as in H.263 version 2. However, the encoding time is about three times longer because of complex operations. In this thesis, a new architecture for full-search variable-size block-matching motion estimation was proposed. The processing element in PE array can deal with variable block sizes in 7 macroblock types in H.26L. Besides, with the consideration of the dataflow and memory accessing, all components in the architecture can work efficiently. The chip implemented by CIC 0.35 μm 1-Poly 4-Metal CMOS technology works at 60 MHz. The Maximum throughput is 29 frames per second in QCIF format with 5 reference frames and 7 block types at 60 MHz.