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High Level Equivalence Symmetric Inputs Identification
Thesis

High Level Equivalence Symmetric Inputs Identification

Ming-Hong Su
Masters, 國立清華大學, 資訊工程學系
2004

Abstract

邏輯驗證 邏輯合成 對稱性輸入 logic verification logic synthesis BDD maximal symmetric inputs sets Nonequivalence symmetry Equivalence symmetry
Symmetry input identification is an important technique in technology mapping, logic synthesis, and . Previous approaches deal with this problem by building BDD and developing algorithms to determine symmetric inputs. For the design whose corresponding BDDs cannot be built, BDD-based approaches cannot be applied on this problem. To avoid the limitations of BDD-based approach, simulation-based methods have been proposed. It is applicable to arbitrary level design description, especially to high level and black box design description. Previous simulation-based approaches focus on determining nonequivalence symmetry. In this paper, we propose a simulation-based approach to identify equivalence symmetric inputs. The experimental results on a set of ISCAS-85 and MCNC benchmarks demonstrate the effectiveness of our algorithm.

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