Abstract
In a modern System on Chip (SoC) design, hundreds of cores and Intellectual Properties (IPs) can be integrated into a single chip. To be suitable for high-performance interconnects, designers increasingly adopt advanced interconnect protocols which support novel mechanisms of parallel accessing including outstanding transactions and out-of-order completion of transactions. To implement those novel mechanisms, a master tags an ID to each transaction to decide in-order or out-of-order properties. However, these advanced protocols may lead to a deadlock problem that does not occur in traditional protocols. To prevent the deadlock problem, current solutions stall suspicious transactions and in certain cases, many such stalls can cause serious performance penalty. In this paper, we propose a novel ID assignment mechanism which guarantees the issued transactions to be deadlock-free and results in significant reduction in the number of stalls. Our experimental results show encouraging performance improvement compared to previous works with little hardware overhead.