Abstract
In this thesis, we have presented two partitioning approaches for a die-stacking SiP design. First, we use Integer Linear Programming (ILP) based method to solve this problem. Second, we use Simulated Annealing (SA) based method to solve this problem. Our SiP partitioning goal is to minimize total length of inter-layer connections, total I/O pads, onchip wire-length and temperature in order to get better performance. The experimental results on the Gigascale Systems Research Center (GSRC) benchmarks show that our SA based method improves the total length of inter-layer connections by 0.31%-7.72%, total I/O pads by 0.34% - 3.13%, temperature by 0.83% - 11.74% and on-chip wire-length by 0.05% - 2.8% compared with hmetis [10].