Abstract
In this paper, we present an Elliptic Curve Cryptographic (ECC) core dedicated to performing point scalar multiplications over GF(2m). The core consists of multiple Arithmetic Units (AUs), a squarer, a controller, and storage devices. Multiple AUs can execute in parallel to perform the crucial operations of ECC, i.e., the point scalar multiplication. The parallelism efficiently speeds up the performance of the scalar multiplication. The proposed high-performance architecture is based on the Montgomery ladder method. In order to raise the utilization of AUs and achieve high speed by reducing cycles, we carefully schedule the field operations for a single iteration of the point scalar multiplication to make AUs as busy as possible. Besides, we exploit the data forwarding technique between arithmetic devices to decrease approximately 15% of the number of cycles. To reduce the critical path delay, the multiplication and the modular reduction are implemented separately in different cycles. We reduce about 13% of the critical path delay in our design. We also induce the bit-parallel modular reduction equations for irreducible pentanomials. The developed bit-parallel modular reduction can operate the modular reduction more efficiently than traditional reduction method. Using 0.13μm CMOS technology, our ECC core can implement a point scalar multiplication with coordinate conversion in 7.7μs at 243.9MHz and in 11.4μs at 242.6MHz over GF(2^163) and GF(2^233), respectively, exhibiting that our result reaches the best performance among all the other published literatures with the same technology. We also explore our architecture with different configurations, i.e. the number of AUs, the cycles needed for a binary field multiplication, and the field size, to find the optimized one under given constraints.