Abstract
The main focus of this work is to design high speed frequency dividers based on currently CMOS 0.18□m technology. A new topology analog divider called Source-degeneration Injection-Locked Frequency divider (SILFD) is proposed. The divider is based on a MOS switch coupled to the sources of the cross coupled pair of well-known LC oscillator. With the varactors and source degeneration, the oscillation frequency and locking rang increase efficiently. The incident signal is provided through the switch transistor, which can be designed much smaller than conventional. The maximum operating frequency is 24.8GHz and the locking range is about 5GHz as input power is 5dBm. The total power consumption is almost 17mW. Besides, a digital frequency divider with feedback resistor is designed. The designed frequency divider uses feedback resistor to increase the operation frequency and has the smaller chip area under the operation frequency which is 18GHz. The locking range is about 2.5GHz as input power is 0dBm. The total power consumption is almost 45mW. This thesis also investigates the effect of substrate noise on circuit characteristics, including the comparison of an ILFD output performances with the noise injected via several different pads. The IM2 and IM3 linearly increase with noise power injection and saturate at noise power near 20~25dBm. As input power of the divider increases, the IM spur would be suppressed. Furthermore, the effect of the inductor grounded or floated on an ILFD is compared and discussed in this thesis also. It is demonstrated the grounded inductor guard ring provides a better immunity from substrate noise than the floated one by 5dBm.