Abstract
The inductive peaking technique is effective to broaden the bandwidth, but it requires a large chip area. In this thesis, two high speed miniaturized CMOS equalizers up to 20 Gb/s are proposed for wireline communications. The equalizers are discussed regarding the design, simulation, and measurement results. Firstly, a 20 Gb/s miniaturized equalizer is realized in 90nm CMOS process. To compensate the coaxial cable loss of 10 dB (~ 3 meters) at 10 GHz, the equalizer incorporates folded active inductors with capacitive and resistive degeneration. Compared to the conventional active and spiral inductors, the folded active inductor consumes lower voltage and occupies less area. The circuit consumes 45mW from a 1.2 V supply, and only occupies 0.14 × 0.28 mm2. The measured maximum peak-to-peak jitter for 18, 19, and 20 Gb/s PRBSs are 14, 13, 15 ps, respectively. Next, another 20 Gb/s miniaturized analog equalizer using 3D solenoid inductors is presented. The equivalent capacitance of the 3D solenoid inductor is much smaller than that of the typical stacked inductor. According to the measurement results, the self-resonance frequency of the 3D solenoid inductor exceeds that of the stacked inductor by 10 GHz with the same area and inductance. In addition, the area of the 3D solenoid inductor is 1/36 times smaller than that of the spiral inductor with the same inductance. Hence, utilizing the small area of 3D solenoid inductor can reduce the size of the chip and lower the cost. The circuit, fabricated in 90nm CMOS process, consumes 14 mW from a 1.2 V supply, and only occupies 0.21 × 0.26 mm2.