Abstract
We have to face a lot of technical difficulties and physical limitations as process fol-lows Moore’s Law continuously. These challenges include increasing of wire RC delays, rising of leakage and manufacturing challenges. 3D integration has the most potential to solve these problems and provide outstanding performance and high density at the same time. But there are many issues surfaced such as the heavy loading of TSV, large TSV pitch and multi-layer addressing. Therefore, how to improve the transfer performance and provide efficiency circuit architectures has been an important issue. In order to demonstrate the advantages of 3D integration, we can satisfy various system requirements using pre-designed logic and different stacking number of memory with universal memory capacity concept. In the thesis, we proposed Self-Timed Differential-TSV Signal Transfer Scheme to reduce the speed penalty of TSV and support the multi-layer stacking function at the same time. On the other hand, the effect of TSV process variation can be reduced also. A 32kb 2 layer 3D-SRAM macro has been fabricated in 0.18um bulk CMOS technology to verify the idea of this work. The measurement results demonstrate that this design can support 20 layers stacking at least and reduce the access time penalty about 34.3% in 20 layers staking compare to single end transfer scheme.