Abstract
Since the next-generation wireless communication systems target to achieve high data rate and high transmission reliability, research on design and implementation of the channel codec becomes a challenging issue. The Turbo code is one of the most popular channel coding schemes for digital communication systems. In this thesis, a high-throughput Turbo decoder for 3GPP-LTE system is proposed. Both the parallel sub-block processing and radix-16 modified Log-MAP algorithm are used to minimize the performance loss, and the word length shortening technique is proposed to reduce the complexity. Besides, the supportability of variable block size is also accomplished by the proposed instruction-based interconnection circuits with instruction ROM. The instructions are pre-processed by the proposed contention-free oriented memory remapping algorithm. Related to the parallelism degree, the proposed remapping algorithm enables the contention-free feasibility with parallelism degree larger than 16, which is larger than that of the QPP interleaver in 3GPP-LTE Turbo decoding. The radix-16 reduced complexity MAP processor is designed and implemented as a single chip, and the proposed variable-block-size Turbo decoder with one raidx-16 MAP processor is realized as a prototype on FPGA module. The well-verified chip using 90nm UMC CMOS technology and Faraday cell library can achieve 571 Mb/s data rate with 392k gate counts. Moreover, the Turbo decoder is also synthesized with the same design kit. It has the throughput of 35.24Mb/s with 8 iterations, and the energy efficiency of this decoder is 0.14 nJ/b/iter.