Abstract
Non-volatile memory plays an important role to store the code and data in today’s SOC chip. In non-volatile memory, the NOR-type flash memory needs fast and reliable random read access due to the code jumps from one memory location to another in code execution. However, the transistor threshold voltage mismatch is more apparent which makes the poor yield and large speed penalty in the advance nanometer technology. To achieve high speed and high yield purposes, we propose a current sense amplifier with offset compensation schemes. The offset compensation schemes include Precharge PMOS Trimming and Bias Trimming, the Precharge PMOS Trimming reduces the mismatch of precharge current and current mirror; the Bias Trimming reduces the mismatch of current sense amplifier. In proposed trimming, we do the calibration after chip fabrication. And set the optimized trim code to flash memory. Furthermore, we use symmetric array and replica reference scheme in this work. The symmetric array reduce loading mismatch between cell side and reference side for high speed sensing; the replica reference scheme use average reference current technique to decrease the reference current variation due to PVT variation. We design a 90nm CMOS technology within 1Mb SuperFlash memory. The experiment result shows that the random read access time is 3ns at sense amplifier supply voltage is 1.2V. Besides, the proposed offset compensation schemes improve 67% random read speed than without offset compensation. The power consumption is 1.23mW in 30MHz.