Abstract
Static Random Access Memories (SRAM) provide an fast data storage and access for most of today's digital IC's, and thus their access time is important for these IC’s performance. However, due to technology improvement the word-line (WL) pulse of the far-end cells is observed to be severely distorted due to large interconnect RC delay. And the interconnect is predicted to get worse in the future. Thus, it is important to solve this problem for technology development. In this thesis, a block forward body bias method to overcome the interconnect delay issue is developed. This method is different from the general bias-based assist methods, which tend to improve the read and write margins. We use the forward body bias to improve the pass gate (PG) and pull down (PD) transistors of the far-end cells to reduce the read access time. A side effect of the forward body bias is the increase of standby current. Partition the SRAM columns into blocks and apply only necessary body bias to each block can trade-off the performance gain with standby current increase. It is demonstrated using 28nm 256k SRAM that the SRAM performance can be improved by 11%, while the standby current increase is reduced by more than 70% compared to full SRAM forward body bias.