Abstract
Modern electronic devices become more and more useful, emphasizing on multifunctional, small size, light weight, etc. as the feature size of logic device has been scaled continuously, conventional inversion-mode Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) face a lot of challenges such as random dopant fluctuation, physical limitation and short channel effect (SCE). Junctionless FET is the one of the solution in the future devices. JL-FET is a novel device, which has heavily doping channel with the same type to that of source and drain. Therefore, JL-FE has a slight (SCEs) and less thermal budget in process of fabrication. In this thesis, hybrid p-channel poly-Si Junctionless field-effect transistors with trench and gate-all-around structure are proposed and fabricated. The hybrid structure makes the thinner effective channel thickness owing to the depletion layer by the channel and substrate. Besides, the annealing after depositing the thick amorphous silicon and use the anisotropic reactive ion etch to form the polycrystalline silicon (poly-Si) UTB. The RIE thinning process could get larger grain size and less grain boundary than directly depositing the thin-film. After RIE thinning process, the nanowires look like the trench structure and the raise S/D structure is completed at the same time.. In addition, gate-all-around (GAA) structure combine with UTB could improve gate control ability, which improve sub-threshold swing (SS) and reduce OFF-state leakage current. The hybrid poly silicon channel junctionless field-effect-transistors with trench structure have ten nanowires with gate-all-around structure. The performance of the device is excellent with the steep sub-threshold swing (SS) (136mV/dec.), the high current ratio (Ion/Ioff current ratio>106), and lower DIBL (60mV/V); then, discuss the electrical characteristics in variable temperature with every 25oC as a step from the 50oC to 200oC, finally, we use Sentaurus TCAD to compare trench structure with without trench structure, the result shows use trench structure can get higher ION/IOFF ratio than without trench structure. The proposed hybrid JL-FETs with trench structure not only the easy fabrication but also has the good characteristics for advanced low power consumption applications and three-dimensional (3-D) stacked ICs applications.