Abstract
AbstractIn order to reduce design time, the reusable IP cores become primary design trend. Issue about delay fault testing becomes more important because of the high performance requirement in VLSI chip. To achieve high performance, VLSI chips need to work correctly at the rated clock. The IEEE 1500 standard provides a standard test interface, and the IEEE 1450.6 standard defines the way to reuse test information. Cooperating with IEEE 1450.6, the IEEE 1500 makes the testing of pre-design IP based SOC easier. In this thesis, a clock controller and a test controller are proposed to support multiple delay testing and to communicate the clock controller and the IEEE 1500 wrapper, respectively. The experimental result shows acceptable area overhead of 0.3% compared with modern SOC, and test time is reduced about 25% when applying parallel test without any test coverage loss.