Abstract
AbstractFollowing the rapidly increasing capacity of semi-conductor technology, the design methodology has come to a higher level of abstraction. The so-called system-on-chip design concept emphasizes reusability of building blocks and provides higher productivity. However, one of issues for the newly-emerging design concept is to verify the products’ functionality and timing specification. IEEE P1500 is applied to test functional correctness of each core in SOC. While verifying the timing specification, the existing wrapper is needed to be modified to carry out delay fault testing of individual core. In this thesis, a delay-fault-testing architecture that consists of modified wrapper based on IEEE P1500 standard and delay-test-aware clock controller is proposed. Wrapper is modified to recreate the environment of delay fault testing for embedded cores, while the clock controller is for test localization. The result shows acceptable area overhead in example SOC design.