Abstract
IR drop has become a critical issue recently because of the increase in the circuit size and supply current density, and it will degrade the circuit performance. The present power models for IR drop (or power supply noise) estimation usually lack accuracy due to neglect of input patterns, cell current waveform and cell location, or they cost too much time for larger circuits. In this thesis, we propose a power grid analysis method based on cell current waveform characterizations to estimate the maximum IR drop. In the process, we create the cell characterization library considering delay, slope, and current waveform with different input patterns by HSPICE simulation. Furthermore, we consider each cell current waveform and cell location to determine the current source for each cell after logic simulation and cell characterization assignment. Finally, we use a first-order iterative method to calculate the maximum IR drop in the power network. Additionally, our method has an extra feedback loop to recalculate the IR drop by the modified cell delay because IR drop will affect the original cell delay. The experimental results show that our simulator is at least 10000 times faster than Nanosim, a common circuit-level simulator, and the average error is only about 7.98%. In addition, we also show the results of maximum IR drop estimation and longest path delay increase for scan test and random pattern simulation by different qualities of power network.