Abstract
Design verification at system level has been one of the most important and challenging jobs for system design. It is because that traditionally, hardware and software are often developed separately. The sequential process of hardware and software development increases time-to-market. In addition, a system-on-chip comprises of many components such as processors, timers, busses, memories and embedded software. Designs are getting bigger in size and larger in complexity. Furthermore, hardware often implement at the RTL level, the simulation of which take much time. These demand designers to describe designs at higher levels of abstraction. The purpose of this thesis is to investigate and practice system level integration and verification. We use JPEG2000, an image compression standard as a design vehicle to explore many system verification problems using SystemC. The major contributions of this thesis are summarized as follows. First, we implement/verify the EBCOT hardware design. To speedup the design, we have use pixel skipping, column based operation and pipeline techniques. The second contribution of this thesis is to build the entire system of JPEG2000 using both systemC and RTL verilog. The system allows us to verify the correctness of software and hardware together, and we can use this system to do lossless compression. Finally, we have integrated and performed simulation on both the SystemC and Verilog together. The platform used for integration is a tool called Cocentric.