Abstract
Embedded systems have been widely applied in communication, multimedia, and many other fields such as consumer electronics. With the applying constraints on cost and power consumption, the requirement of short time-to-market, and the demand of performance, the adoption of high-end programable processors has become more common than ever. Traditionally application specific integrated circuits (ASIC) are no longer sufficient to satisfy the increasing needs. Hence new methodology on design have evolved. Hardware/software co-design are taking places in order to optimize the design flow. The architecture description languages (ADL) of higher abstract levels are utilized to describe the behavior or structure of the processor. And computer automation tools are utilized to synthesize the hardware as well as to generate the software toolchain for design space exploration from the specification defined in the ADLs. At design space exploration, various combinations of design parameters are chosen and each is evaluated for the requirements applied from the specifications. Tradeoffs might be made during the many iterations in the design flow. The software toolchain is essential for this design process to enable the early evaluation of the design. A software toolchain contains a simulator, an assembler, and the linker. Also may be included are the debugger and the profiler. To evaluate the performance achievement on the target application, a compiler is certainly needed. The implementing of the new software toolchain might cost many manpower and take a long development time. Hence an automation approach to generates the tools is desirable. Many efforts have been made to address on the various challenges and some solutions are achieved. However, we are not satisfied with the retarget compiler solutions. There are two major expectations for the retargetable compilers for the design space exploration. First is that the code quality has to be acceptable otherwise the evaluation process could not yield convincible references. The other is that the retargeting process should be accomplished fast, i.e., in a few days. Even though the code quality is not comparable to the well-tuned compiler, it is still competitive since it does not required many months of work to adjust small modifications. We choose to retarget the GNU C compiler (GCC) with the architecture description languages. We can benefit the already existing optimization mechanisms embedded in the compiler system to obtain acceptable code quality. The framework of the compiler architecture enables it comparable simpler to retarget new architectures. GCC is published under the GNU Public Licence and has been commonly accepted as a reference compiler system on many platforms. Proposed in this thesis is a novel approach to generate GCC machine description (MD) from architecture specifications in the language of an ADL. It consists of two stages. First stage is the parsing of the ADL description codes into the GCC register transfer language (RTL), that is actually the intermediate representation of GCC compiler system. The second stage is the MD generation pass, which matches the parsed RTL with standard name patterns of GCC and produces the instruction patterns for GCC in the `.md' file. The core of the system consists of a database of instruction matching rules, which are constructed in three major ways: 1) collected from existing MDs of more than 40 architectures, 2) manually edited matching rules, and 3) inducted rules with other software suits. Besides, the machine parameters such as contained resources and pipeline constraints are analyzed and written into the GCC machine macros, the other part of the MD. We hope this research can lead to the establishment of the interface of the transformation from the architecture description languages to the GNU C compiler, and contribute to the paradigm shift on the System-on-Chip (SoC) design methodology. Rather than being only a code generation system for a mature processor architecture, a compiler system has been a key component of the toolchains for the design space exploration.