Abstract
Design verification has become a bottleneck of modern designs and dominates the whole VLSI design process. Recently, simulation-based random verification has attracted a lot of interests due to its effectiveness in uncovering obscure bugs and due to its automation in generating large vectors. Designers are often required to provide the input probabilities while conducting the random verification. However, it is extremely difficult for designers to provide accurate input probabilities. In this thesis, we propose an algorithm that derives good input probabilities such that the design intent can be exercised effectively for functional verification. We conducted experiments on several combinational and sequential benchmark circuits. The experimental results are very promising.