Abstract
We proposed an architecture for the front-end part of a JPEG2000 image decoder including marker handler, arithmetic decoder and coefficient bit modeling module. The whole JPEG2000 decoder system is made up of the proposed architecture, an IDWT block and an RGB-to-BMP format converter. We have completed the RTL design and verified its functional correctness with gate-level simulation. The circuit has been synthesized targeting toward a 0.35 μm CMOS cell library. Its area is 24,700 gates and speed is 40 MHz.