Abstract
Due to the growing link quality demand of multiple-input multiple-output (MIMO) wireless communication system, traditional QR decomposition-based sub-optimal MIMO detectors gradually cannot support enough bit error rate (BER) performance. In addition, lattice reduction algorithm is proposed to make sub-optimal MIMO detectors achieve the full diversity gain. However, due to the growing number of antennas, the hardware cost and the processing time become a big challenge for hardware design. In this thesis, joint QR decomposition and lattice reduction algorithm is proposed to get better BER performance than only processing QR decomposition. Because both QR decomposition algorithm and lattice reduction algorithm should use Givens rotation processor, this proposed algorithm can combine both two algorithms to do the computation sharing and reduce the hardware cost. In addition, the proposed algorithm removes some unnecessary operations to reduce the computational complexity by joint consideration of this two algorithms. Moreover, the proposed algorithm uses the parallel processing scheme to shorten the processing time. The proposed processor was implemented by TSMC 90nm 1P9M CMOS technology. The proposed processor can supply several different operating modes. According to the post-layout simulation result, the maximum throughput of 8x8 QR decomposition is 2.77 M matrix/s, the maximum throughput of 8x8 lattice reduction is 1.24 M matrix/s and the maximum throughput of joint QR decomposition and lattice reduction for 8x8 MIMO system is 0.856 M matrix/s. In addition, this process can achieve 234.72 M bps (bit per second) in 3rd Generation Partnership Project Long Term Evolution Advanced (3GPP LTE-Advanced) standard at the best case. Although this throughput cannot achieve the maximum throughput demand in 3GPP LTE-Advanced standard, the proposed design can do real-time implementation and achieve the throughput requirement without the limitation of hardware area.