Abstract
The 60GHz band is an excellent choice for wireless applications requiring gigabit-plus data rates, and due to the growing link quality demand of multiple-input multipleoutput (MIMO) wireless communication system, traditional MIMO precodings gradually cannot support enough bit error rate (BER) performance. In addition, lattice reduction algorithm is proposed to make MIMO precodings achieve the full diversity gain. However, due to the growing number of antennas, the hardware cost and the processing time become a big challenge for hardware design. In this thesis, lattice reduction aided Tomlinson-Harashima precoding algorithm is proposed to get better BER performance than only processing Tomlinson-Harashima precoding. Because both lattice reduction and Tomlinson-Harashima precoding algorithm have several similar operations, the proposed algorithm combines both two algorithms to do the computation sharing and reduce the hardware cost. Furthermore, the proposed algorithm revises some unnecessary operations to reduce the computational complexity by joint consideration of this two algorithms. Moreover, the proposed algorithm supply for different kinds of channel characteristics. The proposed processor can supply several different operating modes. The proposed processor was implemented by TSMC 90nm 1P9M CMOS technology. According to the synthesis simulation result, the maximum throughput of 4×4 Tomlison-Harashima precoding is 560 M bps(bit per second), the maximum throughput of 4 × 4 lattice reduction (stage number is 6) aided Tomlison-Harashima precoding is 232 M bps.