Abstract
In the modern semiconductor memory, NAND flash plays an important role to data storage. It can achieve high cell density and low cost with the smallest cell area in the planar semiconductor memory. To develop up-to-date product, increasing the density and decreasing the bit cost have turned into the top target. The state-of-the-art of modern NAND flash technology has reached 2X nanometer. The technology scaling has become more and more difficult and expensive. In order to conquer the restriction, the three dimensional (3D) NAND flash technology has been regarded as the solution of the next generation large data storage application in the recent year. The three dimensional (3D) differs from the planar NAND flash memory; each layer has their unique environment. Hence the initial VTH distribution and the temperature coefficient are different from the other layers as well. The endurance of NAND flash cell will degrade if we keep applying the same program verification voltage to all layers. To reach the goal of layer aware program verification and temperature compensation, we proposed a Bit-Line-clamp (BL-clamp) Generator that should be used with reverse sensing scheme. This proposed circuit can storage several datas that contains the initial VTH difference between target and reference layer combine with the temperature compensated voltage for target layer. And then transferring these datas to the Bit-Line-clamp transistors of each page buffer (PB) simultaneously. In the conventional way, the temperature compensated voltage is applying to the WL. However, each WL is connected to all layers in the three dimensional vertical gate (3DVG) structure. This proposed circuit offers the different compensated voltage to each layer will greatly improve the accuracy and memory endurance.