Abstract
In this thesis we provide a link between gate-level diagnosis and defect-based diagnosis to pinpoint the exact physical locations of the defects. Physical defects are converted into equivalent sub-circuits at logic domain based on a butterfly structure. Diagnostic test pattern generation is formulated as a stuck-at fault detection problem that can be piggybacked on SAT solver. Experimental results indicate that we can reduce 86% possible defect locations and pinpoint the actual locations of the defects for ISCAS85 benchmark circuits. Once the cell defect library is constructed, the proposed method can be applied to any cell-based design without additional stress.