Abstract
We propose an iterative (IR) and simulated-annealing (SA) based methodology for leakage power minimization by the means of gate sizing and threshold voltage assignment. Currently, there is a strong market for high-performance mobile devices to have low power consumption. Among many low power consumption oriented design techniques, leakage power minimization is one of the key technologies. For cell-based design, gate sizing and threshold voltage assignment can be employed to meet timing requirement while reducing total leakage power. We apply simulated-annealing-based optimization on an initial solution that is generated by an iterative algorithm. In order to explore more solution space, we implement a timing engine for fast calculation of timing slack. Experimental results show that the proposed methodology can effectively reduce leakage power under performance constraints.