Abstract
Redundancy Addition and Removal (RAR) and ATPG/Diagnosis-based Design Rewiring (ADDR) are both restructuring techniques used in the synthesis and optimization of logic designs. The RAR adds some redundant wires or gates to the circuit and results in the removal of target wires while the ADDR injects some errors (i.e., removes target wires) and corrects them to make the functionality of the circuit intact. The ADDR is a complete rewiring algorithm by running diagnosis and ATPG algorithms, and provides a wide variety of logic transformations than RAR does. The necessity of verification for validating the restructuring operation, however, is a drawback in the ADDR algorithm. Thus, this paper proposes a novel restructuring technique, Error Injection and Correction (EIC), which formally constructs a corresponding rectification network to the error due to the target wire removal. Since the EIC does not involve diagnosis and ATPG/verification processes, it could improve the run time as compared with ADDR in theory at the expense of missing some restructuring potential. The EIC is also extended to deal with additional types of restructuring operations, including wire addition and gate replacement for achieving more diverse circuit restructuring.