Abstract
To optimize computer program in compiling time, the Open Research Compiler (ORC) provides a well integrated optimization framework with two phases of optimizations. One is the machine level applied on Intermediate Representation for Code Generation (CGIR), which is a machine level of Intermediate Representation (IR) with one to one mapping instructions. The other is the source level phase applied on Winning Hierarchical Intermediate Representation Language (WHIRL). This thesis gives an overview of ORC, introduces the compiler architecture that implemented in ORC and the evolution of ORC, and illustrates how these compiler phases work including the IR flow and the compilation process. The research is focused on two optimizations in the WHIRL level, Loop Nested Optimization (LNO) and Interprocedural Optimization (IPA). The theoretical concepts, algorithms and the way practiced in ORC are individually illustrated. Besides, LNO and IPA are ported to a new specific architecture, Parallel Architecture Core (PAC) Digital Signal Processor (DSP). The solved porting process and issues are presented in detail. The experiments of LNO and IPA are conducted on the proposed platform to show interesting results and to demonstrate performance improvements.