Abstract
Elliptic curve cryptography (ECC) become one of the most popular public-key cryptography recently. On the same security level with RSA, ECC has shorter key length. Base on this property, ECC is more suitable for RFID tags which has limitations in space and power. In our approach, we propose an low-cost architecture to support the crucial operation over GF(2m) of ECC, that is to say, the point scalar multiplication. The core consists of Arithmetic Unit (AU), a controller, and storage devices. The proposed AU includes a high-radix multiplier, an adder and a bit-parallel squarer. In order to minimize the space resource by decreasing complexity of multiplexers, we integrate the components of AU to eliminate selections of input and use circular register file architecture to limit the register access. To attain low power consumption, the design need to work at low clock frequency. Based on the Montgomery ladder algorithm, we carefully schedule the field operation of point scalar multiplication to simplify register management. Also, the use of bit-parallel squarer decreases about 47% of the number of cycles. Besides, we find trade-off between space and power with register management restrictions. The implementation result with TSMC 65nm CMOS technology shows that the proposed design requires an area of 12,859 gates, and has a power consumption of 4.64 μW to perform a scalar multiplication over GF(2163) in 250ms at 102kHz. The advantage of hardware cost is much favorable compared with previous similar works.