Abstract
Due to the growing data rate and link quality requirements in recent years, the MIMOOFDMtechniques are developed to satisfy these demands. Unlike the high hardware cost like the optimal ML detector needs, the application of lattice-reduction (LR) technique can assist the sub-optimal detectors improve the detection performance with significantly lower hardware cost compare with ML demands. However, the FFT-size LR operations and QR decomposition still cause a big burden for hardware implementation if the QR-based MIMO detectors are applied. In this thesis, the adoption of interpolation-based QR decomposition (IQRD) of the proposed architecture can release the large hardware cost problem caused by QR decomposition and the cooperation of IQRD with preprocessing LR scheme make the coherent property between sub-carriers is efficiently utilized. In order to make the proposed design is applicable to various of channel environments, the processing stage number of the E-CTLLL operations are set adjustable. In addition, when the appropriate separated choices are applied, the group scheme makes this design only affected by the channel correlation characteristic in each group. For efficient hardware implementation, some processors and calculations with lower hardware cost are substituted for original ones. Furthermore, the proposed design devoted to promoting the hardware utilization rate of processors to reduce the hardware cost with sufficient throughput. Actually, according to the synthesis results by utilizing Synopsys Design Compiler with the Arm cell library and TSMC 90nm CMOS technology, the throughput of the proposed design can achieve 6.592 M matrix/s in the best case (MS = 6; S = 2 in EPA channel) with gate count 220.68k.