Abstract
Non-volatile memory plays an important role to store the code and data in today’s SOC chip. In non-volatile memory, NOR flash memory is designed for code programming, while NAND flash memory is usually used to data storage and designed for high throughputs. When it is strongly demanded for high capacity data storage equipment, it is very important that how to implement a high density and low cost non-volatile memory. Developing three dimension memory is one of the most popular solutions. Because the cell current of three dimension memory is usually much smaller than planar memory, we decide to use the All Bit Line Architecture after comparing the performance of many sense amplifiers. It has to spend more area implementing the All Bitline Architecture comparing with other sensing schemes, therefore we simplify the All Bitline Architecture appropriately, and propose the disturbance free precharge scheme to overcome the defect of simplified circuit. We fabricate a 256Mb NAND flash memory in 75nm, 3D VG TFT BE-SONOS technology. The proposed sensing circuit improves 23.1% layout area and results in about 2.27% read throughputs penalty and 0.28% energy consumption penalty than All Bitline Architecture without any simplified. At the 3.3V supply voltage, the read, program, program verify, erase, and erase verify are all functional in our measurement.